control-clock

CLI reference

glasgow run control-clock

Generates a 50% duty cycle square wave with a specified frequency by dividing the FPGA system clock. Achievable frequencies are integer fractions of 24 MHz (for revC and later).

usage: glasgow run control-clock [-h] [-V SPEC] [--clk PIN] [-f FREQ]

-h, --help

show this help message and exit

-V <spec>, --voltage <spec>

configure I/O port voltage to SPEC (e.g.: ‘3.3’, ‘A=5.0,B=3.3’, ‘A=SA’)

--clk <pin>

bind the applet I/O line ‘clk’ to PIN (default: ‘A0’, required)

-f <freq>, --frequency <freq>

set clock frequency to FREQ kHz (default: 1000)

API reference

class glasgow.applet.control.clock.ClockDriveInterface(logger: Logger, assembly: AbstractAssembly, *, clk: GlasgowPin, name: str = 'clk')

async enable(frequency: int) → int

Enable and configure clock.

Sets the clock frequency to frequency Hz and configures the clock pin as push-pull. If the clock pin is already configured as push-pull, then the change in frequency is done as follows: the current half-cycle has the old period, and the next half-cycle has the new period.

Returns the actual frequency used, which may be equal or less than frequency.

async disable()

Disable clock.

Disables the oscillator and configures the clock pin as Hi-Z.