qspi-analyzer

glasgow run qspi-analyzer

Capture transactions on the extended variant of the SPI bus with four I/O channels.

QSPI data is captured in a clock domain driven by the SCK pin and reset by the CS# pin. This approach enables capturing data at very high SCK frequencies (up to 96 MHz), but requires a small delay between the last SCK rising edge and CS# rising edge, otherwise the last byte of a transaction will not be captured correctly. Typically, QSPI controllers do provide this delay.

Signal integrity is exceptionally important for this applet. When using flywires, twist every signal wire (at the very least, CS# and SCK wires) with a ground wire connected to ground at both ends, otherwise the captured data will likely be nonsense.

Both quad-IO and dual-IO captures are supported. If only IO0 and IO1 pins are provided, the capture proceeds as if IO2 and IO3 were fixed at 0.

The capture file format is Comma Separated Values, in the following line format:

• <DATA>, where <DATA> is a hexadecimal nibble sequence with each four bits corresponding to samples of HOLD#, WP#, CIPO, COPI (from MSB to LSB).

If your DUT is a 25-series SPI Flash memory, use the tool memory-25x to extract data from capture files. If quad-IO commands are not in use, the spi-analyzer applet can reduce the likelihood of an overflow.

usage: glasgow run qspi-analyzer [-h] [-V SPEC] [--cs PIN] [--sck PIN]
                                 [--io PINS] [--buffer-size BYTES]
                                 [FILE]

file

save communications to FILE as hex sequences

-h, --help

show this help message and exit

-V <spec>, --voltage <spec>

configure I/O port voltage to SPEC (e.g.: ‘3.3’, ‘A=5.0,B=3.3’, ‘A=SA’)

--cs <pin>

bind the applet I/O line ‘cs’ to PIN (default: A0)

--sck <pin>

bind the applet I/O line ‘sck’ to PIN (default: A1)

--io <pins>

bind the applet I/O lines ‘copi’, ‘cipo’, ‘wp’, ‘hold’ to PINS (default: A2,A3,A4,A5)

--buffer-size <bytes>

set FPGA trace buffer size to BYTES (must be power of 2, default: 16384)