`program-ice40-sram`¶

CLI reference¶

glasgow run program-ice40-sram¶

Program the volatile bitstream memory of iCE40 FPGAs.

usage: glasgow run program-ice40-sram [-h] [-V SPEC] [--cs PIN] [--sck PIN]
                                      [--copi PIN] [--reset PIN] [--done PIN]
                                      [-f FREQ]
                                      BITSTREAM

bitstream¶: bitstream file

-h, --help¶: show this help message and exit

-V <spec>, --voltage <spec>¶: configure I/O port voltage to SPEC (e.g.: ‘3.3’, ‘A=5.0,B=3.3’, ‘A=SA’)

--cs <pin>¶: bind the applet I/O line ‘cs’ to PIN (default: ‘A0’, required)

--sck <pin>¶: bind the applet I/O line ‘sck’ to PIN (default: ‘A1’, required)

--copi <pin>¶: bind the applet I/O line ‘copi’ to PIN (default: ‘A2’, required)

--reset <pin>¶: bind the applet I/O line ‘reset’ to PIN (default: ‘A3’, required)

--done <pin>¶: bind the applet I/O line ‘done’ to PIN (default: ‘A4’, optional)

-f <freq>, --frequency <freq>¶: set SCK frequency to FREQ kHz (default: 12000)

API reference¶

exception glasgow.applet.program.ice40_sram.ICE40SRAMError¶

class glasgow.applet.program.ice40_sram.ICE40SRAMInterface(logger: Logger, assembly: AbstractAssembly, *, cs: GlasgowPin, sck: GlasgowPin, copi: GlasgowPin, reset: GlasgowPin, done: GlasgowPin | None = None)¶

property clock: ClockDivisor¶: SCK clock divisor.

async load(bitstream: bytes | bytearray | memoryview) → bool¶

Load bitstream into configuration SRAM.

Raises:: ICE40SRAMError – If the CDONE pin is present and was not asserted within 100 ms after the bitstream has been shifted in.